It is well known that when digital signals in parallel form have to be transmitted at a certain distance, it is preferable to convert them into serial form so as to be able to utilize a single transmission line, instead of as many lines as are the bits of the parallel signal, for instance eight. The signal to be transmitted must furthermore be appropriately coded in order to minimize its sensitivity to any interference which may have been collected by the transmission line and to enable the receiving apparatus to check the correctness of the received datum. Naturally, upon reception the signal has to be reconverted into the original (parallel) form in order to be utilized.
Digital signals to be transmitted, coded in a parallel mode and, generally, in NRZ (Non Return to Zero) format, must undergo a first coding of the 4B/5B type, which, by making a 5 bit block correspond with each 4 bit block, allows enlargement of the number of transitions of the transmitted signal. In particular, this coding guarantees the occurrence of at least one logic level transition for each 4 bits transmitted, avoiding the risk of a loss of synchronism of the receiving equipment by the presence in the signal of long stays at the same logic state. Moreover, the possible reception of one of the 16 not utilized 5-bit codes may be used for the detection of errors in the received signal.
After the 4B/5B coding, the parallel signal has to be converted into series mode and into the NRZI (Non Return to Zero Inverted) format, adopted internationally.
The NRZ/NRZI format converter causes the digital signal to be changed over between the two logic states, at the clock signal rate, when the NRZ signal remains at level one, whereas it causes it to stay at 0 or at 1 (depending on the last transition performed), when the NRZ signal is at logic state 0.
In reception, it is necessary to read correctly the received data, extracting from them the clock signal for the detection, and thus perform the inverse conversion and decoding operation, checking for the presence of any possible transmission errors.
The extraction of the clock signal is usually performed utilizing a PLL (Phase Locked Loop) circuit, which uses as a reference signal the same numerical signal arriving at the receiver and provides at the output side a clock signal at a frequency that is twice the bit rate. The arriving signal constitutes a good reference signal if it is rich in level transitions, so that its frequency spectrum has a precise component at the bit repetition frequency. This component is usually extracted by means of pass-band filters of the LC or SAW (Surface Acoustic Wave) type. These filters are rather bulky, they cannot be integrated with circuits on the same chip and they reduce the flexibility of the device, as they do not allow frequency excursion.
Another difficulty derives from electromagnetic compatibility problems due to the need to integrate on the same chip at least two PLL circuits, one in reception for the extraction of the clock signal and another one in transmission for the multiplication of the system clock signal for the serialization of the digital signal. Naturally on the same chip there may be more than one transceiver, and several PLL circuits, each with its own VCO (Voltage Controlled Oscillator), operating at radio frequency simultaneously with the others and thus being a source of electromagnetic radiation. Therefore it is necessary to adopt a precise topological strategy, at the design stage, concerning the placement of the circuits on the chip, in order to minimize disturbances and interference.
Finally, the device has to be able to operate at rather high bit rates, which currently are around 200 Mbit/s, maintaining at the same time reduced power consumption.
A transceiver that is able to carry out the aforementioned functions, called HOT-ROD, has been realized by Gazelle in GaAs technology, and can reach considerable bit rates, but is very expensive and inefficient. The ratio between the devices that are actually in operation and those produced is only about 20%, while for devices realized on silicon it reaches 80%.
A transceiver of this type may also be realized utilizing bipolar technology integrated circuits, such as those denominated SP9970 and SP9930 by GEC Plessey. The former integrated circuit contains a series-to-parallel converter, a parallel-to-series converter and a PLL that performs the multiplication by 10 of system frequency, whereas the latter one contains a PLL for the extraction of the clock signal and a NRZ/NRZI converter. Moreover, other circuits for the 4B/5B coding/decoding and the detection of errors are required.
With these circuits too the attainable bit rate is good, but the power consumption, typical of bipolar technology, is rather high.
Both examined solutions allow the extraction of the clock signal without the use of external filters, substituted by appropriate PLL circuits comprising a main loop (master) and a slaved one (slave), as described for example in the paper "A BiCMOS Receive/Transmit PLL Pair for Serial Data Communication", by Barry L. Thompson et al., presented at IEEE 1992 Custom Integrated Circuits Conference or in the paper "A Self Correcting Clock Recovery Circuit", by Charles R. Hogge, published in the Journal of Lightwave Technology, no. 6, December, 1985. The master loop recovers the fundamental frequency of the system starting from a reference frequency, while the slave loop brings about small phase corrections as a function of the received signal.
However, this type of PLL circuit presents some problems, as the two VCOs disturb each other, causing spurious locks.